/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2018-2019.
 * Description: cache_extend.S
 * Author: liujianping <jianping.liu@huawei.com>
 * Create: 2018-09-06
 */

#include <asm/ptrace.h>
#include <asm/asm-offsets.h>
#include <asm/page.h>
#include <asm/pgtable-hwdef.h>
#include <asm/thread_info.h>
#include <linux/errno.h>
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/cpufeature.h>
#include <asm/alternative.h>

/*
 * Save/disable and restore interrupts.
 */
	.macro	save_and_disable_irqs, olddaif
	mrs	\olddaif, daif
	disable_irq
	.endm

	.macro	restore_irqs, olddaif
	msr	daif, \olddaif
	.endm

/*
 *	__flush_dcache_all()
 *
 *	Flush the whole D-cache.
 *
 *	Corrupted registers: x0-x7, x9-x11
 */
__flush_dcache_all:
	dmb	sy				// ensure ordering with previous memory accesses
	mrs	x0, clidr_el1			// read clidr
	and	x3, x0, #0x7000000		// extract loc from clidr
	lsr	x3, x3, #23			// left align loc bit field
	cbz	x3, finished			// if loc is 0, then no need to clean
	mov	x10, #0				// start clean at cache level 0
loop1:
	add	x2, x10, x10, lsr #1		// work out 3x current cache level
	lsr	x1, x0, x2			// extract cache type bits from clidr
	and	x1, x1, #7			// mask of the bits for current cache only
	cmp	x1, #2				// see what cache we have at this level
	b.lt	skip				// skip if no cache, or just i-cache
	save_and_disable_irqs x9		// make CSSELR and CCSIDR access atomic
	msr	csselr_el1, x10			// select current cache level in csselr
	isb					// isb to sych the new cssr&csidr
	mrs	x1, ccsidr_el1			// read the new ccsidr
	restore_irqs x9
	and	x2, x1, #7			// extract the length of the cache lines
	add	x2, x2, #4			// add 4 (line length offset)
	mov	x4, #0x3ff
	and	x4, x4, x1, lsr #3		// find maximum number on the way size
	clz	w5, w4				// find bit position of way size increment
	mov	x7, #0x7fff
	and	x7, x7, x1, lsr #13		// extract max number of the index size
loop2:
	mov	x9, x4				// create working copy of max way size
loop3:
	lsl	x6, x9, x5
	orr	x11, x10, x6			// factor way and cache number into x11
	lsl	x6, x7, x2
	orr	x11, x11, x6			// factor index number into x11
	dc	cisw, x11			// clean & invalidate by set/way
	subs	x9, x9, #1			// decrement the way
	b.ge	loop3
	subs	x7, x7, #1			// decrement the index
	b.ge	loop2
skip:
	add	x10, x10, #2			// increment cache number
	cmp	x3, x10
	b.gt	loop1
finished:
	mov	x10, #0				// swith back to cache level 0
	msr	csselr_el1, x10			// select current cache level in csselr
	dsb	sy
	isb
	ret
ENDPROC(__flush_dcache_all)

/*
 *	flush_cache_all()
 *
 *	Flush the entire cache system.  The data cache flush is now achieved
 *	using atomic clean / invalidates working outwards from L1 cache. This
 *	is done using Set/Way based cache maintenance instructions.  The
 *	instruction cache can still be invalidated back to the point of
 *	unification in a single instruction.
 */
ENTRY(flush_cache_all)
	mov	x12, lr
	bl	__flush_dcache_all
	mov	x0, #0
	ic	ialluis				// I+BTB cache invalidate
	ret	x12
ENDPROC(flush_cache_all)

hnf_pstate_poll:
        /* x0 has the desired status, return only if operation succeed
         * clobber x1, x2, x6
         */
        mov     x1, x0
        mov     w6, #8                  /* HN-F node count */
        mov     x0, #0x18
        movk    x0, #0x420, lsl #16     /* HNF0_PSTATE_STATUS */
1:
        ldr     x2, [x0]
        cmp     x2, x1                  /* check status */
        b.eq    2f
        b       1b
2:
        add     x0, x0, #0x10000        /* move to next node */
        subs    w6, w6, #1
        cbnz    w6, 1b
        ret

hnf_set_pstate:
        /* x0 has the desired state, clobber x1, x2, x6 */
        mov     x1, x0
        /* power state to SFONLY */
        mov     w6, #8                  /* HN-F node count */
        mov     x0, #0x10
        movk    x0, #0x420, lsl #16     /* HNF0_PSTATE_REQ */
1:      /* set pstate to sfonly */
        ldr     x2, [x0]
        and     x2, x2, #0xfffffffffffffffc     /* & HNFPSTAT_MASK */
        orr     x2, x2, x1
        str     x2, [x0]
        add     x0, x0, #0x10000        /* move to next node */
        subs    w6, w6, #1
        cbnz    w6, 1b

        ret

ENTRY(llc_clean_inv_all_armccn)
        /*
         * Return status in x0
         *    success 0
         */
        mov     x29, lr

        dsb     sy
        mov     x0, #0x1                /* HNFPSTAT_SFONLY */
        bl      hnf_set_pstate

        mov     x0, #0x4                /* SFONLY status */
        bl      hnf_pstate_poll

        dsb     sy
        mov     x0, #0x3                /* HNFPSTAT_FAM */
        bl      hnf_set_pstate

        mov     x0, #0xc                /* FAM status */
        bl      hnf_pstate_poll

        mov     x0, #0
        mov     lr, x29
        ret
ENDPROC(llc_clean_inv_all_armccn)
